Parallel Read-Out High-Speed Input Buffer ATM Switch Architectures

The prototype first in first out (FIFO) input buffer asynchronous transfer mode (ATM) switch is known as the architecture on which the transfer capacity is considerably limited, and is necessary to be given some improvement. In this paper, a novel parallel read-out structure is introduced to the input buffer ATM switch design to remove such the above limitation. Transfer performances of cell traffics on the novel switch with the three control rules of a cyclic read-out (CRO) cell selection, a parallel read-out random (PROR) cell selection, and a parallel read-out maximum (PROM) queue selection are evaluated by simulations. The simulation results show that the introduced parallel read-out structure gives a drastic buffer size reduction. Especially, PROR and PROM architectures totally offer large amounts of hardware reductions though small hardware increments may be required for paralleling. Consequently it is shown that PROR and PROM input buffer switches give loss performances lower than that of the corresponding output buffer switches with the same level transfer delays.